1. Technical Field
The Invention disclosed broadly relates to FET circuits and more particularly relates to improvements in FET binary counter circuits.
2. Background Art
Synchronous binary counters avoid rippling of a carry bit from a low order position to a higher order position by providing logic decoding at the inputs of the higher order positions which combine the presence of the input clocking signal with the condition of the lower order bits so as to determine whether the bit at a particular position should be changed. Prior art synchronous counters include those described in U. S. Pats. Nos. 3,992,635; 3,943,378; and 3,657,557. Although these prior art synchronous counters accomplish the function of anticipating the need for high order carry bits, circuit delays imposed by these circuits render them too slow for high speed counting applications.
To begin this description, several terms need to be defined and suitable abbreviations established. The N channel field effect transistor circuit technology will be the example used herein. The abbreviation "NFET" will be used herein to refer to an N channel field effect transistor device. Such devices are generally fabricated by forming an N-type conductivity source diffusion and N-type conductivity drain diffusion in the surface of a P-type conductivity silicon substrate. The channel region of the substrate separating the source and the drain regions is covered by a gate insulator layer and the gate electrode. An enhancement mode NFET is normally nonconducting between its source and drain and it can be switched into conduction by applying a positive potential to its gate electrode, with respect to the potential of it source electrode. A depletion mode NFET is normally coducting between its source and drain and it can be switched into nonconduction by applying a negative potential to its gate electrode, with respect to the potential of its source.
The threshhold potential for an FET device can be adjusted by means of ion implantation or other well-known techniques so that the potential difference between the gate and the source of the FET device can be selectively made more positive in the case of enhancement mode FET devices, or more negative in the case of depletion mode FET devices. If the threshhold voltage of an FET device is selectively adjusted so that conduction starts when there is no potential difference between the gate of the device and its source, then such a device is referred to as a zero threshold or "natural" threshold FET device.
When current is conducted from the drain to the source of an FET device, the electric potential at the source is reduced from the electric potential at the drain of the device by a quantity substantially equal to the threshold voltage for the device. Thus, for enhancement mode FET devices which typically have a threshold voltage of a positive one volt, when positive current is conducted from the positive drain to the less positive source of the device, the electric potential at the source is reduced from the electric potential at the drain of the device by a quantity of approximately one volt. In contrast, for a zero threshold or "natural" threshold FET device, when positive current is conducted from the drain to the source of the FET device, there is substantially no reduction in the electric potential at the source of the device.
Large scale integrated circuits and very large scale integrated circuits developed in the prior art have proved to be difficult to test because of embedded combinatorial logic positioned between sequential logic elements or latches. The prior art developed the technique of level sensitive scan design (LSSD) in order to test embedded combinatorial logic by means of selectively scanning in sequences of binary bit test patterns into an input latch stage, clocking the scanned-in data through the combinatorial logic for one cycle, and then scanning out the resultant binary bits from an output latch stage connected to the output of the combinatorial logic. This tecnhique has been described in detail, for example in U. S. Pats. Nos. 3,761,695; 3,783,254; and 3,806,891 by Eichelberger, all assigned to the IBM Corporation.
Occasionally herein it will be necessary to refer to binary logic variables and complementary binary logic variables. The use of the "*" notation herein following the expression for a binary logic variable, will indicate the binary complement of that variable. A positive logic convention will be used herein, where a more positive potential is considered representing a binary "1" value and a less positive potential is considered representing a binary "0" value.